In the semiconductor device manufacturing industry, efforts are continuing for the purpose of further downsizing a single package semiconductor device. The initial effort for the purpose of realizing miniaturization of a semiconductor device reduced the size of the semiconductor chip itself. By making the semiconductor chip smaller, the number of chips that could be obtained from one wafer was increased, and alone with bringing down manufacturing costs, since the movement distance of electrons between each element could be made shorter, the operating speed was increased. Due to the development of microscopic processing technology, decreasing the chip size for a semiconductor device having the same functions became possible. The current leading-edge design guideline is less than 0.18 μm, and by this means, it has become possible to place more than two million units on a single semiconductor chip.
In order to realize a miniaturization of the semiconductor device, the next effort involved making the size of the package in which a chip is sealed as close as possible to the size of the semiconductor chip it houses. As one result related to this effort, a type of semiconductor device was created called a chip size package (Chip Size Package:CSP) or a chip scale package (Chip Scale Package). The connecting terminals (for example, solder balls, hereinafter, called external connecting terminals) for the printed circuit board on which the semiconductor device is mounted form a two-dimensional arrangement on the face of a semiconductor chip, and was successful in bringing the size of the package close to the chip size. By decreasing the above-mentioned package size so as to approach the semiconductor chip size, along with the mounting surface area becoming small, the wiring length that connected the terminals on the chip and the external connecting terminals became short, and by this means, in the same manner as when decreasing the size of above-mentioned semiconductor chip itself, the operating speed of the semiconductor device was increased.
However, even when the package size was decreased, the manufacturing cost could not be lowered very much. Because various processes for the packaging were conducted for each individual semiconductor chip cut out from the wafer, even if the package size was decreased, because the number of processes was fixed, there were no changes in productivity.
With this background, technology that packages a semiconductor chip as is in the wafer state (hereinafter, called wafer level CSP) has been proposed, and development is continuing in the direction of its realization by individual companies. Semiconductor manufacturing technology that executes packaging at a stage before individual semiconductor chips are cut away from the wafer is referred to as wafer level CSP. In wafer level CSP, since the packaging process can be done as one unit with the wafer process, the packaging cost, and by extension, the manufacturing cost of the semiconductor, can advantageously be greatly lowered. In regard to the further detailed content of wafer level CSP, please refer to the “Nikkei BP Company publication, Nikkei Micro-device, 1998 August Issue, Pages 44 to 71.”
On the one hand, in a wafer level CSP, in the same manner as in a conventional CSP type semiconductor device, there are problems in mounting reliability in relation to the printed circuit board. In thermal cycle tests of this type of semiconductor device, cracks are generated in the junction portion of the external connecting terminals of the printed circuit board, and there are instances when the junction is open and defective. The main cause is stress based on linear expansion coefficient differences between the semiconductor chip made of silicon and the printed circuit board made of FR4 or the like, and a means that relieves this must be devised in the design for a wafer level CSP.
Thus, as a method that absorbs the linear expansion coefficient difference between the above-mentioned semiconductor chip and the printed circuit board, and by this means relieves the stress, a construction has been proposed wherein a metallic supporting post is formed on the wiring pattern of the semiconductor chip main face, and an external connecting terminal comprising a solder ball or the like is bonded on top of the said supporting post. In said semiconductor device, the main face of the above-mentioned semiconductor chip and the surrounding of the supporting post are covered by resin. Due to the fact that the above-mentioned supporting post is interposed between the external connecting terminal that is directly bonded to the printed circuit board and the semiconductor chip, the generation of the above-mentioned stress can be relieved by means of deformation of said supporting post element.
However, a semiconductor device that is equipped with the above-mentioned metallic supporting posts has the following types of problems.
(1) Time and expense are required in forming the metallic supporting posts on the main face of the semiconductor chip. In other words, the above-mentioned metallic supporting posts are formed by means of accumulating a metal plating (for example, copper plating) on the wiring pattern. In order to relieve the above-mentioned stress, it is necessary for said supporting posts to have a height of more than 100 μm, and more than two h are required to form these supporting posts by means of the plating method. In order to further improve the mounting reliability for the semiconductor device, it is necessary to further heighten the supporting posts, (for example, to more than 200 μm), and realization of that is extremely difficult from the aspects of time and cost.
(2) In the case of forming the metallic supporting posts by means of a plating method, because their shape and material cannot be freely selected, the degree of freedom for the design of the target package is limited
Therefore, the objective of this invention, in a semiconductor device referred to as a wafer level CSP, is to improve its productivity while ensuring its mounting reliability.